These tools are useful for protecting your laptop, enhancing connectivity, managing files and media, and/or customizing your Windows laptop. And most of them are free. Let's start with security downloads. Apps for your laptop
Wednesday, June 15, 2011
Monday, June 13, 2011
Friday, June 10, 2011
Thursday, May 19, 2011
Evaluation of PDK in semi conductor industry
Process Design Kit (PDK) is the interface between semiconductor design tools and the semiconductor manufacturing process. For each new process we need to bring up PDK. Initially PDK referred to a PCELL library supplied by a foundry. PDK’s eventually grown to include all design elements, docs etc related technology which ever necessary for IC design.
Contents of PDK: Manufacturing design rules, electrical design rules and DRC, LVS run set files to verify physical & electrical layout for various EDA tools. Schematic symbol libraries. Various kinds of simulation models. Parasitic extraction rules. Description of basic building blocks of the process and are expressed algorithmically as Parameterized cells (PCells). Call backs to execute, evaluate and update when changes to parameters. Schematic symbols, PCells and callbacks are linked via a Component Description Format (CDF). Layer map file & technology file for layout Editors.
Essence of iPDK: PDK’s were specific to EDA vendors, specific to foundry, tech node & process variant. With more number of tools & more number of processes it’s became a very difficult situation for qualifying PDK’s to all combinations. So Interoperable PDK Libraries Alliance (IPL) working with TSMC explored the possibility of interoperable PDK’s (iPDK), PDK that can supports different EDA tools.
Need of common database: To get iPDK it’s important to have a common data base for EDA companies. To interoperate without data conversion and loss of functionality in between any two different EDA tools. A standard database Open Access (OA) created by cadence and given to the Silicon Integration Initiative (Si2) for standards organization.
Need of common scripting language: PCell coding for iPDK, there is a necessary of interoperable scripting language. The OA standard features plug-ins for many of standard scripting languages like Tcl, C++ and Python. Ciranova created OA based Python PCells called PyCells.
Why Python? Python supports OOPs. Faster run times. PyCell code has fewer lines as compared to PCell code. It also supports features like abutment, stretch handles and DFM rules. Efficient PyCell debugging to shortening cycle times.
Contents of PDK: Manufacturing design rules, electrical design rules and DRC, LVS run set files to verify physical & electrical layout for various EDA tools. Schematic symbol libraries. Various kinds of simulation models. Parasitic extraction rules. Description of basic building blocks of the process and are expressed algorithmically as Parameterized cells (PCells). Call backs to execute, evaluate and update when changes to parameters. Schematic symbols, PCells and callbacks are linked via a Component Description Format (CDF). Layer map file & technology file for layout Editors.
Need of common database: To get iPDK it’s important to have a common data base for EDA companies. To interoperate without data conversion and loss of functionality in between any two different EDA tools. A standard database Open Access (OA) created by cadence and given to the Silicon Integration Initiative (Si2) for standards organization.
Need of common scripting language: PCell coding for iPDK, there is a necessary of interoperable scripting language. The OA standard features plug-ins for many of standard scripting languages like Tcl, C++ and Python. Ciranova created OA based Python PCells called PyCells.
Why Python? Python supports OOPs. Faster run times. PyCell code has fewer lines as compared to PCell code. It also supports features like abutment, stretch handles and DFM rules. Efficient PyCell debugging to shortening cycle times.
iPDK is seen as TSMC standard. But other foundries wont support it. They only support virtuoso PDK. Si2 has started a new effort to develop Open Process Design Kit (Open PDK). The goal of Open PDK is to define a set of open standards to allow a PDK to be portable across foundries and EDA tools.
Wednesday, May 18, 2011
12 Social Networking Services
Now a days social networks became a part of every one's life.
Here you can find 12 social network to stay in connection with your family, friends & colleagues.
See the slide show in below link for more details : 12 Social Networks
Here you can find 12 social network to stay in connection with your family, friends & colleagues.
See the slide show in below link for more details : 12 Social Networks
Monday, May 16, 2011
Crossing the barriers: Through Silicon Via (TSV)
Through Silicon via (TSV) technology is a 3D integration of multiple dies into a single stack to transfer data among the dies.
TSV is composed of a conductor, crossing the Si Subtrate of the stacked dies. This conductor is electrically insulated from the substrate by a dielectric and connects the metal wires of the stacked dies.
Cross Section of TSV:
Advantages of TSV technology:
TSV technology uses vertical interconnections (where as 2D IC's use only horizental interconnects). As it use small area of 3D ICS's leading to shorter wirelength than 2D IC's because gates can be placed on top of each other in different dies, eliminating the need of long chip interconnects existing in 2-D IC's.
TSV among different dies:
TSV is composed of a conductor, crossing the Si Subtrate of the stacked dies. This conductor is electrically insulated from the substrate by a dielectric and connects the metal wires of the stacked dies.
Cross Section of TSV:
Advantages of TSV technology:
TSV technology uses vertical interconnections (where as 2D IC's use only horizental interconnects). As it use small area of 3D ICS's leading to shorter wirelength than 2D IC's because gates can be placed on top of each other in different dies, eliminating the need of long chip interconnects existing in 2-D IC's.
- Greater density for the same footprint
- More functionality
- Higher performance
- Lower power consumption
- Lower cost
- More manufacturing flexibility
- Faster time to market
TSV among different dies:
Thursday, May 12, 2011
EDA Tools from various vendors to check DRC
EDA Vendors
| Tool | Vendor | Features |
| Calibre nmDRC | Mentor Graphics | Hierarchical DRC, multi-core, gold standard at many foundries |
| Calibre Pattern Matching | Mentor Graphics | DRC+ graphical input, multi-core, supports Globalfoundries 28nm node |
| Calibre InRoute | Mentor Graphics | DRC and DFM while doing P&R with Olympus |
| Calibre RealTime | Mentor Graphics | DRC inside of IC layout editors |
| Hercules | Synopsys | Hierarchical, for 45nm nodes and larger |
| IC Validator | Synopsys | Hierarchical, for 45nm nodes and smaller, validated at 40nm nodes, multi-core, integrates with IC Compiler |
| IC Compiler | Synopsys | DRC and DFM with IC Validator while doing P&R with IC Compiler |
| PVS | Cadence | Multi-core |
| In-Design PVS | Cadence | Multi-core, integrates with P&R and Custom IC layout editor |
| Quartz DRC | Magma | Multi-core, Quartz DRC GUI, integration with Talus® Vortex allows for in-the-loop incremental DRC |
| Talus qDRC | Magma | Integration with Talus® Vortex allows for in-the-loop incremental DRC |
| HiPer Verify | Tanner EDA | Lower cost, DRC for AMS designs, reads decks from: Calibre, Assura, Dracula |
| PowerDRC | Polyteda | Flat full-chip DRC, multi-core |
Subscribe to:
Posts (Atom)
